Embodiments of the present invention generally relate to methods and apparatus for selective formation of epitaxial layers containing silicon and carbon. Specific embodiments pertain to methods and apparatus for the selective formation of n-doped epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
The amount of current that flows through the channel of a MOS transistor is directly proportional to a mobility of carriers in the channel, and the use of high mobility MOS transistors enables more current to flow and consequently faster circuit performance. Mobility of the carriers in the channel of an MOS transistor can be increased by producing a mechanical stress in the channel. A channel under compressive strain, for example, a silicon-germanium channel layer grown on silicon, has significantly enhanced hole mobility to provide a pMOS transistor. A channel under tensile strain, for example, a thin silicon channel layer grown on relaxed silicon-germanium, achieves significantly enhanced electron mobility to provide an nMOS transistor.
An nMOS transistor channel under tensile strain can also be provided by forming one or more carbon-doped silicon epitaxial layers, which may be complementary to the compressively strained SiGe channel in a pMOS transistor. Thus, carbon-doped silicon and silicon-germanium epitaxial layers can be deposited on the source/drain of nMOS and pMOS transistors, respectively. The source and drain areas can be either flat or recessed by selective Si dry etching. When properly fabricated, nMOS sources and drains covered with carbon-doped silicon epitaxy imposes tensile stress in the channel and increases nMOS drive current.
To achieve enhanced electron mobility in the channel of nMOS transistors having a recessed source/drain using carbon-doped silicon epitaxy, it is desirable to selectively form the carbon-doped silicon epitaxial layer on the source/drain either through selective deposition or by post-deposition processing. Furthermore, it is desirable for the carbon-doped silicon epitaxial layer to contain substitutional C atoms to induce tensile strain in the channel. Higher channel tensile strain can be achieved with increased substitutional C content in a carbon-doped silicon source and drain.
Generally, sub-100 nm CMOS (complementary metal-oxide semiconductor) devices require a junction depth to be less than 30 nm. Selective epitaxial deposition is often utilized to form epitaxial layers (“epilayers”) of silicon-containing materials (e.g., Si, SiGe and Si:C) into the junctions. Selective epitaxial deposition permits growth of epilayers on silicon moats with no epitaxial growth on dielectric areas. Selective epitaxy can be used within semiconductor devices, such as elevated source/drains, source/drain extensions, contact plugs or base layer deposition of bipolar devices.
A typical selective epitaxy process involves a deposition reaction and an etch reaction. During the deposition process, the epitaxial layer is formed on a monocrystalline surface while a layer of polycrystalline and/or amorphous material is deposited on at least a second layer, such as an existing polycrystalline layer and/or an amorphous layer. The deposition and etch reactions occur simultaneously with relatively different reaction rates to an epitaxial layer and to a polycrystalline layer. However, the deposited polycrystalline/amorphous layer is generally etched at a faster rate than the epitaxial layer. Therefore, by changing the concentration of an etchant gas, the net selective process results in deposition of epitaxy material and limited, or no, deposition of polycrystalline material. For example, a selective epitaxy process may result in the formation of an epilayer of silicon-containing material on a monocrystalline silicon surface while no deposition is left on the spacer.
Selective epitaxy deposition of silicon-containing materials has become a useful technique during formation of elevated source/drain and source/drain extension features, for example, during the formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. Source/drain extension features are manufactured by etching a silicon surface to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown epilayers, such as a silicon germanium (SiGe) material. Selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during silicide formation increases the series resistance even further. In order to compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction. Typically, the elevated source/drain layer is undoped silicon.
However, current selective epitaxy processes have some drawbacks. In order to maintain selectivity during present epitaxy processes, chemical concentrations of the precursors, as well as reaction temperatures, must be regulated and adjusted throughout the deposition process. If not enough silicon precursor is administered, then the etching reaction may dominate and the overall process is slowed down. Also, harmful over-etching of substrate features may occur. If insufficient etchant precursor is administered, then the deposition reaction may dominate, reducing the selectivity to form monocrystalline and polycrystalline materials across the substrate surface. Also, current selective epitaxy processes usually require a high reaction temperature, such as about 800° C., 1,000° C. or higher. Such high temperatures are not desirable during a fabrication process due to thermal budget considerations and possible uncontrolled nitridation reactions to the substrate surface. In addition, most of the C atoms incorporated through typical selective Si:C epitaxy processes at the higher process temperatures occupy non-substitutional (i.e. interstitial) sites of the Si lattice. By lowering growth temperature, a higher fraction of substitutional carbon level can be achieved (e.g. nearly 100% at growth temperature of 550° C.), however, the slow growth rate at these lower temperatures is undesirable for device applications, and such selective processing might not be possible at the lower temperatures.
The manufacturing conditions for silicon carbon epitaxy may be different for epitaxy having different dopants and dopant concentrations. The incorporation of high levels of dopants (e.g. greater than 1020 atoms/cm3) into the Si:C epitaxy during deposition is of interest, because the incorporation of high levels of dopants during deposition reduces the need to increase the dopant level using subsequent procedures such as ion implantation. Taking into consideration the wide array of variables in an epitaxial manufacturing process including, but not limited to, temperature, carrier gas type, deposition gas type, etching gas type, flow rates for each of the etching, deposition and carrier gases and chamber pressure, the selection and optimization of specific variables for a particular epitaxy having a specific dopant and dopant concentration can be unpredictable. Thus, the incorporation of high levels of dopants into the Si:C epitaxy may require changing a large number of variables to achieve high quality epitaxy. It would be desirable to provide process for forming heavily n-doped Si:C epitaxy. Such methods would be useful in the manufacture of transistor devices.